project

TRNG WebApp — Ultra96

Networked True Random Number Generator  /  Avnet Ultra96 · Zynq UltraScale+ MPSoC ZU3CG

live

Last value received

{
  "status": "waiting for the board to report…"
}

overview

What is it?

dataflow

From silicon to the network

Entropy is generated and conditioned entirely in the programmable logic. The PS only triggers a run, reads two words over AXI4-Lite, scores the raw bits and ships the payload over HTTPS.

ring oscillators ─XOR─► rnd_bit ─► trng_assemble ─► random[439:0]
   (ro_cell × n_ro)                                  │
                                                     ├─► sha256_stream440 ─► hash[255:0]
                                                     │
        PS (PetaLinux) ◄──AXI4-Lite── trng_axi ◄──────────┘
              │
              ├─ NIST SP 800-90B health (RCT + APT) on the 440 raw bits
              └─ POST { id, trng256, trng_stream, health, temperature } ─► lut7.dev

internals

Entropy pipeline

The ring oscillators are the entropy source; everything from XOR reduction through SHA-256 conditioning runs in the FPGA fabric, leaving the PS to validate and publish.

rtl

The entropy source — in Verilog

At the heart of the PL design is a bank of ring oscillators. Each one is a closed loop of LUT-based inverters mapped to Xilinx LUT1 primitives; their outputs are XOR-reduced to a single bit and registered onto the synchronous clock.

module ro_trng #(
  parameter n_ro = 64
) (
  input  wire aclk,     /* system clock */
  input  wire resetn,   /* synchronous active-low reset */
  output reg  rnd_bit   /* one random bit per aclk cycle */
);

  wire [n_ro-1:0] ro_out;

  /* n_ro free-running ring oscillators (LUT1 primitives) */
  genvar i;
  generate
    for (i = 0; i < n_ro; i = i + 1) begin : gen_ro
      ro_cell u_ro (
        .out (ro_out[i])
      );
    end
  endgenerate

  /* XOR reduction sampled into the synchronous domain */
  always @(posedge aclk) begin
    if (!resetn)
      rnd_bit <= 1'b0;
    else
      rnd_bit <= ^ro_out;
  end

endmodule

All resets are synchronous and the design uses a single posedge aclk domain. Combinational ring-oscillator loops are explicitly waived in the XDC so the synthesiser does not optimise them away.

hardware

Target & toolchain

validation

NIST SP 800-90B health tests

Two continuous tests run on the raw 440-bit word, before the SHA-256 conditioning — hashing would mask a broken source by turning even a constant input into random-looking output. They are cheap, always-on sanity checks that catch a noise source that has died or latched up, not a measure of entropy quality.

web app

The POST payload

After each run the PS sends one JSON document to the web app: the board ID, the 256-bit conditioned value, the full 440-bit raw stream and the health verdict for that read.

{
  "id":          "0x96",
  "trng256":     "4eceb744166401913a861630543b379f6695ee88b9004cb6b6f843a4c1112a6d",
  "trng_stream": "c1ac5e34…d70",   /* 440 raw bits, 110 hex */
  "health":      "OK",                /* OK · WARMING · FAIL_RCT · FAIL_APT */
  "temperature": 42.67
}

Because the health tests are continuous, the host feeds successive reads to one stateful monitor that treats them as a single stream, rather than scoring each 440-bit word in isolation.

usage

On the board

A small Python host script triggers the PL, reads the raw word and its digest over the generic-uio driver, runs the NIST health tests and POSTs the result. Note the APT reporting WARMING until its 512-bit window fills.

measurement

Entropy quality

The continuous tests only detect a broken source. To measure how much entropy a healthy one provides, a 1,000,000-bit capture of the raw ring-oscillator stream was run through the NIST SP 800-90B non-IID estimators on an x86 host.

Ring oscillators never reach 1.0 bit/bit, so 0.74 is a healthy raw rate: 440 × 0.7428 ≈ 327 bits of input min-entropy. Since that exceeds the 256-bit output width, the SHA-256 digest qualifies as full entropy under the SP 800-90B vetted-conditioning rule (confirmed by ea_conditioning: h_out = 256, ε = 2^-78.32), with a ~28 % margin so the design stays above 256 bits even if the source degrades over voltage, temperature or age.